Dynamic Logic Styles with Improved Noise-immunity
نویسندگان
چکیده
Noise issues are becoming an important concern in digital systems due to the aggressive scaling trends in devices and interconnections. To address this problem a new noise-tolerant dynamic circuit technique suitable for dynamic logic styles is presented. Simulation results show that the proposed technique improves the ANTE by 3.4 and 2.8 over conventional dynamic True Single-Phase-Clock (TSPC) and Domino logic, respectively. The improvement in the ANTE-Delay quotient is 2.8 and 2.25 over conventional dynamic logic, 2.0 and 1.7 over Twintransistor technique, 1.7 and 1.04 over Bobba’s technique for CMOS TSPC and Domino AND gates, respectively.
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